Effect of annealing time on Si/SiO2 interface property for CMOS fabricated on hybrid orientation substrate with ATR method

In this work, we report an investigation into the interface property of CMOS devices using hybrid orientation technology (HOT). For nMOSFETs, devices with increased defect-removal annealing time brought about a significant reduction in the charge pumping current and low-frequency noise. This result implies that the amorphization/templated recrystallization (ATR) process-induced defects at the recrystallized (1 0 0) regions are further repaired, and consequently achieved the “low-trap-density” of the Si/SiO 2 interface. On the other hand, for pMOSFETs, no obvious distinction can be observed between devices on both HOT wafers, indicating that the treatment of defect-removal anneal would not affect bonding (1 1 0) regions. In addition, on HOT wafers, the low-frequency noise of pMOSFETs is attributed to a fluctuation in the mobility of free carriers, while the unified model, i.e., the carrier-number fluctuation correlated mobility fluctuation, dominates the low-frequency noise of nMOSFETs. Keywords Annealing Dislocations Defects Interfaces Electrical properties Semiconductors 1 Introduction Recently, because of the strong dependence of carrier mobility on silicon orientation, hybrid orientation technology (HOT) has led to increased interest in the CMOS device and technology community due to the significant performance boost provided by the use of (1 0 0)-oriented Si (the orientation in which electron mobility is higher) and (1 1 0)-orientated Si (the orientation in which hole mobility is higher) for n- and pMOSFETs, respectively [1] , and a current flow in the 〈1 1 0〉 direction provides the highest drive currents for both types of devices [2–4] . Various implementations of this technology have been demonstrated using silicon-on-insulator (SOI) substrates with either one [5] or both [6] types of devices on an insulating layer, but these solutions proposed for the implementation of HOT on SOI require selective epitaxial growth which involves significant process complexity and cost. On the other hand, the amorphization/templated recrystallization (ATR) integration scheme combined direct silicon bond (DSB) substrates technology and solid phase epitaxy (SPE) has been reported by fabricating devices on bulk-Si-like substrate to easily reuse circuit design libraries from the bulk CMOS environment [7,8] . However, ATR process would induce defects (i.e., end-of-range dislocation loops or threads) at the recrystallized (1 0 0)-oriented Si layers, and still existed even through a high temperature defect-removal anneal (>1000 °C). These defects would cause the degradation of gate oxide integrity in nMOSFETs [9] . In this work, the annealing treatment has been modified to further repair the ATR-induced defects and improve the Si/SiO 2 interface quality. The improvement of ATR’d material quality is investigated by the DC, charge pumping and low-frequency noise measurements, simultaneously. 2 Experimental A DSB-HOT was implemented by integrating DSB and ATR process to fabricate bulk n- and pMOSFETs on (1 0 0) and (1 1 0) plane, respectively. Substrates comprised the DSB overlayers of 250 nm thickness of (1 1 0) Si on (1 0 0) Si wafers, which fabricated to give a Si-to-Si interface free of interfacial oxide. Then, the ATR process was performed as shown in Fig. 1 to convert the nMOSFETs regions into (1 0 0)-oriented Si. During ATR process, we used an implant-block mask to protect the pMOSFETs regions while Si + ion implantation (2 × 10 15 cm −2 at 150 keV) was performed for the amorphization. Annealing for recrystallization was subsequently performed in N 2 at 650 °C for 2 h followed by high-temperature annealing at 1050 °C for 2 h to repair the ATR-induced defects (i.e., HOT-A wafer). To investigate the effects of annealing time on the Si/SiO 2 interface property, we also prepared wafers with extra annealing. For these wafers, we changed the defect-removal annealing condition to 1050 °C for 4 h (i.e., HOT-B). For avoiding the defects in the recrystallized Si adjacent to shallow trench isolation (STI), all the wafers underwent a straightforward scheme of ATR before STI. Fabrication of bulk CMOS devices was then carried out. An equivalent oxide thickness of 19 Å was measured for nitrided gate oxide, and a thickness variation of 1 Å was observed across the two crystal planes. The samples were characterized by an on-wafer test using HP-81110A pulse generator and HP-4156C semiconductor parameter analyzer for charge pumping measurement. The low-frequency noise was measured by consisting of a standard research SR570 low noise current amplifier with HP-35670A dynamic signal analyzer. 3 Results and discussion Fig. 2 shows the drain current ( I D ) as a function of drain voltage ( V D ) for n- and pMOSFETs. For nMOSFETs, we observe a 6.1% I D enhancement from the HOT-B wafer under a fixed gate overdrive ( V G − V T = 1.0 V) and V D = 1.0 V. In addition, it can be found that threshold voltage ( V T ) becomes smaller from devices on HOT-B wafer in the linear region. The result implies that the extra annealing process would reduce the ATR-induced defects, resulting in improvement of the Si/SiO 2 interface for nMOSFETs on HOT-B wafer. For pMOSFETs, we find that no appreciable distinction between both HOT wafers. It means that increased defect-removal annealing time would not affect bonding (1 1 0) regions. To evaluate the Si/SiO 2 interface quality, a charge pumping (CP) measurement has been performed to extract the amount of interface state density ( N it ) [10] , as shown in Fig. 3 (a) and (b) for nMOSFETs and pMOSFETs, respectively. It can be found that the N it value of nMOSFETs on HOT-B wafer is lower than that on HOT-A wafer, and the comparable N it value for pMOSFETs between both HOT wafers. These results agree well with the measured DC characteristics. The underlying mechanism responsible for the discrepancy between n- and pMOSFETs can be explained by the following. For nMOSFETs, the (1 0 0) region suffers from the attack of ion-implantation, and defects are induced at the recrystallization layer. The extensive annealing treatment is employed to further repair ATR-induced defects at nMOSFETs regions. Bonafos et al. [11] have reported that the population mean radius of the defects proportionally increase with annealing time while their density decreases through the exchange of Si self-interstitial atoms between the dislocation loops. This can rationalize the observed decrease in ATR-induced defects density using longer defect-removal anneal. With extra annealing, threading defects at recrystallization layers can be suppressed, and not propagate to the wafer's surface. Consequently, we can achieve a better Si/SiO 2 interface. On the other hand, during ATR process, the (1 1 0) region for pMOSFETs fabrication is protected by implant-block mask, and the impact of ATR process on this region is expected to be a little significance. In our case, the comparable Si/SiO 2 interface property of pMOSFETs between both HOT wafers is found, indicating that the treatment of defect-removal anneal would not affect bonding (1 1 0) regions again. The low-frequency noise is another useful tool for characterizing Si/SiO 2 interface in MOSFETs. The inset of Figs. 4 and 5 show normalized drain current noise spectral density ( S ID / I D 2 ) measured between 1 Hz and 10k Hz biased in linear operation for n- and pMOSFETs, respectively. As expected, considerably lower low-frequency noise levels are measured from the nMOSFETs on HOT-B wafer as compared to those measured from the counterparts on HOT-A wafer, while comparable level is observed from pMOSFETs between both HOT wafers. The trap density ( N t ) of 7.90 × 10 16 cm −3 eV −1 extracted from nMOSFET on HOT-B wafer is lower than that on HOT-A wafer (2.46 × 10 17 cm −3 eV −1 ), and, for pMOSFET, the N t of 1.20 × 10 19 are obtained from HOT-B wafer, which is comparable with HOT-A wafer (1.02 × 10 19 cm −3 eV −1 ). These results consist with CP measurement. Besides, it should be worthy to note that the nMOSFETs on HOT-B wafer show a superior quantity of N t as compared to the nanowire nMOSFETs (1.70 × 10 18 cm −3 eV −1 ) [12] and strained-Si nMOSFETs (1.30 × 10 17 cm −3 eV −1 ) [13] , but the N t level of pMOSFETs is still higher than that of counterpart fabricated on (1 0 0) wafer [14] due to the inherent higher density of dangling bonds at the (1 1 0) surface [15] . On the other hand, the low-frequency fluctuations are generally attributed to carrier-number fluctuation, mobility fluctuation and source drain series resistance fluctuation. In our HOT devices, the normalized noise found to be independent of drain bias indicates that the noise source are not due to contact or drain and source series resistance. To determine the physical mechanism of low-frequency noise in HOT CMOS, we plot the normalized power spectral density, S ID / I D 2 , of drain-current fluctuations and the corresponding transconductance to drain current ratio squared, ( g m / I D ) 2 as functions of drain current. As shown in Fig. 4 , it can be found that the S ID / I D 2 curves for both HOT nMOSFETs vary with drain current as the ( g m / I D ) 2 , except for the strong inversion. Therefore, measured low-frequency noise should be related to a unified model, which is the combination of carrier-number fluctuation and mobility fluctuation [16] . For HOT pMOSFETs, a significant departure of the ( g m / I D ) 2 variation in Fig. 5 provides strong evidence to suggest that the mobility fluctuation dominates the mechanism of low-frequency noise [17] . Moreover, the total drain current noise power can be described by a unified model as [16] (1) S id = k T I d 2 γ f W L 1 N + α μ 2 N t where N is the number of channel carriers per unit area, α is the scattering coefficient and μ is the carrier mobility. Eq. (1) reveals that the contribution of carrier-number fluctuation in generating the low-frequency noise is proportional to 1/ N , and the contribution of mobility fluctuation is proportional to αμ . The value of these two parameters extracted from our experimental data is listed in Table 1 . It agrees with our conclusion of low-frequency noise mechanism for HOT n- and pMOSFETs. 4 Conclusion Characterization of the interface properties for HOT CMOS devices is investigated by DC, CP and low-frequency noise measurements simultaneously. The HOT nMOSFETs with increased defect-removal annealing time show the driving current improvement and lower interface trap density, while comparable value in the driving current and interface quality for pMOSFETs can be found. Finally, the behavior of low-frequency noise for devices on HOT wafers is also investigated, and could be described by the mobility fluctuation and unified mode, i.e., a combination of carrier-number fluctuation and mobility fluctuation, for p- and nMOSFETs, respectively. Acknowledgement This work is supported by the National Science Council (NSC) of Taiwan , under Contract No. NSC 99-2221-E-230-019. References [1] M. Yang M. Ieong L. Shi K. Chan V. Chan A. Chou E. Gusev K. Jenkins D. Boyd Y. Ninomiya D. Pendleton Y. Surpris D. Heenan J. Ott K. Guarini C. D’Emic M. Cobb P. Mooney B. To N. Rovedo J. Benedict R. Mo H. Ng IEDM Tech. Dig. 2003 453 [2] M. Yang E. Gusev M. Ieong O. Gluschenkov D. Boyd K. Chan P. Kozlowski C. D’Emic R. Sicina P. Jamison A. Chou IEEE Electron Device Lett. 24 2004 339 [3] M.V. Fischetti Z. Ren P.M. Solomon M. Yang K. Rim J. Appl. Phys. 94 2003 1079 [4] L. Chang M. Ieong M. Yang IEEE Trans. Electron Devices 51 2004 1621 [5] M. Yang V. Chan S.H. Ku M. Ieong L. Shi K.K. Chan C.S. Murthy R.T. Mo H.S. Yang E.A. Lehnef Y. Surprid F.F. Jamin P. Oldiges Y. Zhang B.N. To J.R. Holt S.E. Steen M.P. Chudzik D.M. Fried K. Bemstein H. Zhu C.Y. Sung J.A. Ott D.C. Boyd N. Rovedo Proc. Symp. VLSI Technol. Dig. Tech. 2004 160 [6] M. Yang K. Chan A. Kumar S.-H. Lo J. Sleight L. Chang R. Rao S. Bedell A. Ray J. Ott J. Patel C. D’Emic J. Rubino Y. Zhang L. Shi S. Steen E. Sikorski J. Newbury R. Meyer B. To P. Kozlowski W. Graham S. Maurer S. Medd D. Canaperi L. Deligianni J. Tornello G. Gibson T. Dalton M. Ieong G. Shahidi Proc. Symp. VLSI Technol. Dig. Tech. 2006 131 [7] C.Y. Sung H. Yin H. Ng K.L. Saenger V. Chan S. Crowder J. Li J.A. Ott R. Bendernage J. Kempisty V. Ku H.K. Lee Z.J. Luo A. Madan R.T. Mo P. Nguyen G. Pfeiffer M. Raccioppo N. Rovedo D.K. Sadana J.P. de Souza R. Zhang Z. Ren C. Wann IEDM Tech. Dig. 2005 235 [8] H. Yin C.Y. Sung H. Ng K.L. Saenger V. Chan S. Crowder R. Zhang J. Li J.A. Ott G. Pfeiffer R. Bendernagel S.B. Ko Z. Ren X. Chen G. Wang J. Liu K. Cheng A. Mesfin R. Kelly V. Ku Z.J. Luo N. Rovedo K. Fogel D.K. Sadana M. Khare G. Shahidi IEDM Tech. Dig. 2006 1 [9] K.L. Saenger J.P. de Souza K.E. Fogel J.A. Ott A. Reznicek C.Y. Sung D.K. Sadana H. Yin Appl. Phys. Lett. 87 2005 221911-1 [10] G. Groeseneken H.E. Maes N. Beltran R.F. De Keersmaecker IEEE Trans. Electron Devices 31 1984 42 [11] C. Bonafos D. Mathiot A. Claverie J. Appl. Phys. 83 1998 3008 [12] J. Zhuge R. Wang R. Huang Y. Tian L. Zhang D.-W. Kim D. Park Y. Wang IEEE Electron Device Lett. 30 2009 57 [13] H.Y. Lin S.L. Wu S.J. Chang Y.P. Wang C.W. Kuo Semicond. Sci. Technol. 23 2008 1 [14] K.W. Chew K.S. Yeo S.-F. Chu Solid-State Electron. 48 2004 1101 [15] S. Zafar M. Yang E. Gusev A. Callegari J. Stathis T. Ning R. Jammy M. Ieong Proc. IEEE VLSI-TSA Symp. 2005 128 [16] K.K. Hung P.K. Ko C. Hu Y.C. Cheng IEEE Trans. Electron Devices 37 1990 654 [17] G. Ghibaudo T. Boutchacha Microelectron. Reliab. 42 2002 573