1.1-V, 8-bit, 12 MS/s asynchronous reference-free successive-approximation-register analogue-todigital converter in 0.18 μm CMOS with separated capacitor arrays.

This study presents an 8-bit asynchronous reference-free successive-approximation-register analogue-to-digital converter (ADC). A novel charge recycling method is proposed to decrease the power consumption by switching the two separated capacitor arrays alternatively in the first four phases of one conversion. The last four phases stick to the conventional method. According to the calculation and the MATLAB simulation, 67% energy reduction is obtained. The four largest capacitors in the main array and the two capacitors in the helper array are broken into halves to generate the positive and negative comparison references, respectively. Combining an aggressive unit capacitance layout scheme and the proposed capacitor layout distribution, the matching performance, the geometric shape and the wiring parasitics are improved. The over-sampled system clock is not required with the asynchronous timing control of the successive comparisons. The reference-free configuration utilises power supply and ground instead of two dedicated buffered voltage references. The prototype ADC is fabricated in semiconductor manufacturing international corporation (SMIC) 0.18 μm complementary metal oxide semiconductor (CMOS) process. At 12 MS/s sampling rate and 1.1 V power supply, it consumes 130 μW and achieves a signal-to-noise-and-distortion-ratio of 47.4 dB, resulting in a figure-of-merit of 58.4 fJ/conversion-step and an active area of 0.1 mm2. © The Institution of Engineering and Technology 2013.