Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator for Wireless Receivers

In order to design high performance sigma-delta A/D converters, it is essential to estimate the Figure-Of-Merit in the design process. This paper describes the design of a power/performance efficient single-loop multibit sigma-delta modulator for wireless applications. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. A 3rd order 4-bit Σ − Δ modulator with feedforward path is designed in 0.18um CMOS process operating from 1.8V supply voltage. The modulator dissipates 8.6 mW and achieves a dynamic range of 84/95 dB over a bandwidth of 2000/100 kHz.