Generation of Synthetic Sequential Benchmark Circuits.

Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the effectiveness of new architectures and software. Benchmark circuits arc a precious commodity, and often cannot be found at the correct granularity, or in the desired quantity. In previous work, we have defined important physical characteristics of combinational circuits. We presented a tool (CIRC) to extract them, and gaue an algorithm and tool (GEN) which generates random circuits, parameterized by those characteristics or by a realistic set of defaults. Though a promising step, only a small portion of real circuits are fully combinational. In this paper we extend the effort to model sequential circuits. We propose new characteristics and generate circuits which are sequential. This allows for the generation of truly useful benchmark circuits, both at and beyond the sizes of next-generation FPGAs. By comparing the post-lay out properties of the generated circuits with already existing circuits, we demonstrate that the synthetic circuits are much more realistic than random graphs with the same number of nodes, edges and I/Os.