Designing giga-scale memory systems with stt-ram

Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory technology with the potential to be used as universal memory. The near-SRAM endurance and CMOS compatibility makes it suitable for use throughout the memory and storage hierarchies. However, the density is significantly lower than Flash, and the high write-currents limit the performance and energy-efficiency of STT-RAM caches. This dissertation presents tools and techniques for modeling and optimizing STT-RAM for use in high-speed memory system design. This makes it possible to compare published magnetic tunnel junction (MTJ) designs and perform first-order evaluations of cache and memory designs. Augmenting a Flash-based Solid-State Disk with a STT-RAM merge cache can reduce the response time by more than 75%, while sacrificing the retention-time of the memory cells improves both the performance and energy-efficiency of STT-RAM caches. Detailed error modeling makes it possible to design a refreshing scheme that maintains the reliability of the system, and dynamically adjusting the refresh rate according to current temperature reduces the refresh overhead. This adaptive refreshing can reduce the cell area by more than 28%, compared to STT-RAM with error, while simultaneously limiting the impact of performance and consumption.