A 50nW, 100kbps Clock/Data Recovery Circuit in an FSK RF Receiver on a Body Sensor Node

This paper presents a low power clock and data recovery (CDR) circuit for a wireless body sensor node. The proposed circuit interfaces the RF receiver output with the digital processing. It consumes 50nW at 100kbps. It uses a delay locked loop (DLL) that is calibrated in one-shot fashion to save power, locking over 18X faster than prior art. The proposed circuit is fabricated in a 0.13μm CMOS technology. It recovers data with an input jitter of up to 2.4μs with >2X less power and >2X less area than prior work. The proposed circuit is a synthesizable all digital implementation.