Impacts of device architecture and low current operation on resistive switching of HfOx nanoscale devices

A highly scaling feasibility of resistance memory with a via-hole structure including Ti/HfO"x is demonstrated in this work. An empirical model is used to predict the correlation between the forming voltage of 5nm-thick HfO"x devices with concave configuration and their cell size. The forming voltage of the nano-devices fit well with the empirical model of dielectric breakdown. Owing to the parasitic capacitance of the support oxide, the resistance memory with a series transistor still suffers a serious current overshoot during the forming process. The first reset current in the concave device increase as the scaling down of their cell size. The 30nm concave device with a compliance current of 0.18mA exhibits a good operation window (ON/OFF resistance ratio 30), a satisfactory reliabilities including a thermal stability at 150^oC for 500min lifetime and switching cycles of 10^4. The operation current for 50nm concave device can be lowered to 30@mA. The first reset current in the pillar device through increasing the dielectric thickness in the parasitic capacitance can be eliminated.