The Design and Implementation of a Power Efficient Embedded SRAM

Yijun Liu,Pinghua Chen, Wenyan Wang,Zhenkun Li

PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation（2007）

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摘要

In this paper, a power efficient 2K asynchronous SRAM is presented for embedded applications. The SRAM adopts a low swing write scheme, which greatly reduces the power dissipated by charging and discharging the bitlines. A small dual-rail decoder is proposed to compensate for the extra silicon area needed by the low swing write technique. The new SRAM is demonstrated to a factor of 4 improvement in power efficiency over a commercial SRAM macro. It also 30% faster than the commercial SRAM macro with only 3% area overhead.

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关键词

commercial SRAM macro,low swing,asynchronous SRAM,new SRAM,power efficiency,area overhead,extra silicon area,embedded application,small dual-rail decoder,efficient embedded SRAM

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