Static noise margin analysis of sub-threshold SRAM cells in deep sub-micron technology
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION（2005）
摘要
Reducing leakage current in memories is critical for low-power designs in deep submicron technology. A common architectural technique consists of lowering the supply voltage to operate SRAM cells in sub-threshold (Vth). This paper investigates stability aspects of sub-Vth SRAM cells, both analytically and by simulation in STMicroelectronics' 90nm CMOS technology. For the first time analytical expressions for the Static Noise Margin in sub-Vth as a function of circuit parameters, operating conditions and process variations are derived. The 3G receiver case study illustrates the leakage saving potential of stable sub-Vth SRAM designs resulting into energy savings of up to 65%.
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关键词
sub-threshold sram cell,deep submicron technology,leakage saving potential,energy saving,sram cell,common architectural technique,sub-vth sram cell,circuit parameter,stable sub-vth,static noise margin,deep sub-micron technology,cmos technology,static noise margin analysis,leakage current,process variation,operant conditioning
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