Impact of Circuit Degradation on FPGA Design Security
VLSI（2011）
摘要
SRAM-based Field Programmable Gate Arrays (FPGAs) are used in a variety of security-critical embedded applications. However, soft-error issues, and vulnerability to design plagiarism are two key challenges for SRAM FPGAs in mission-critical commercial products. Encrypted bit streams with keys stored internally in the FPGA are widely used to alleviate the design security risk. In this paper, we introduce how degradation of the device over the course of normal operation can be used as a new form of identifying the stored keys. We also highlight the impact of process variation on the effectiveness of this attack. Finally, we suggest a simple bit-flipping technique to alleviate this problem.
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关键词
process variation,new form,mission-critical commercial product,design security risk,key challenge,encrypted bit stream,sram chips,circuit degradation impact,sram-based fpga,normal operation,security-critical embedded application,simple bit-flipping technique,fpga design security,sram-based field programmable gate,soft-error issue,sram fpgas,field programmable gate arrays,sram-based field programmable gate array,circuit degradation,soft error,reliability,normal operator,field programmable gate array,security,cloning,degradation
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