Network Main Memory Architecture for NoC-Based Chips
Computer and Information Technology（2010）
摘要
Network on Chip (NoC) is considered to be the best candidate for future on-chip communication; however, with the increase in the number of on-chip processors, the simultaneous memory accesses of these processors can cause serious main memory bottleneck problem. In this study, we have proposed the concept of Network Main Memory (NMM). NMM has distributed network architecture for main memory and multicommunication channels to NoC chips, which can overcome the main memory bottleneck problem. When compared with traditional memory, the bandwidth of NMM can be sufficiently used owing to the network architecture, and it is convenient to increase the memory bandwidth. Our experimental results on simulator show that our NMM can provide better traffic for NoCs. In addition, management of NMM as well as the software model for NoC chips and NMM have also been discussed.
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关键词
on-chip processor,serious main memory bottleneck,on-chip processors,distributed network architecture,network main memory,future on-chip communication,traditional memory,software model,simultaneous memory access,main memory,noc-based chips,on-chip communication,main memory bottleneck problem,network on chip,network main memory architecture,multicommunication channels,noc chip,memory bandwidth,network architecture,network-on-chip,communication channels,system on a chip,chip,bandwidth,memory management,network topology
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