A new asynchronous parallel global optimization method based on simulated annealing and differential evolution

This paper presents a new asynchronous parallel global optimization method and its application to the automated device sizing in analog integrated circuit (IC) design. The method is based on the simulated annealing algorithm (SA), but incorporates features from differential evolution (DE) to improve the sampling efficiency and avoid the problems involved with the cooling schedule selection. A simple local search procedure is also incorporated to improve the fine tuning capabilities of the method. To reduce the optimization time, the method is designed as an asynchronous master-slave parallel system that allows simultaneous evaluation of several trial solutions. Comparison with simple SA and DE on a set of well-known analytical test functions confirms the method's efficiency. The parallel efficiency of the method is also verified by optimizing the functions with 1, 2, 4, and 8 processors. The proposed approach is also applied to several real world cases of device sizing in analog IC design. The optimization results indicate that the method is capable of finding near optimal circuits. The parallel efficiency of the method is confirmed with optimization runs on 1, 2, 4, and 8 processors.