PLL modeling and verification in a cycle-simulation environment

Recent advances in technology, computer architecture, and automated design environments have ushered in a new era of computer design in which large complex servers such as the S/390 G5 Parallel Enterprise Server™ can be delivered with times to market once reserved for low-end systems such as single-user workstations and personal computers. Yet, the time to market is inversely proportional to customer demand for reliable and continuously available systems. Therefore, the need exists to build and simulate a complete system which incorporates realistic and accurate behavioral representations for all design components. This paper describes a method for modeling an analog phase-locked loop, interfacing it with digital sequential logic components, and simulating the entire system in a high-performance two-cycle simulation environment. Further discussion demonstrates the role this verification has played in the deployment of an improved design point with a shorter time to market compared to previous genera tions of S/390® CMOS machines.