Tradeoff Between Complexity and Memory Size in the 3GPP Enhanced aacPlus Decoder: Speed-Conscious and Memory-Conscious Decoders on a 16-Bit Fixed-Point DSP

This paper investigates tradeoff between complexity and memory size (speed-memory tradeoff) in the 3GPP enhanced aacPlus decoder based on a 16-bit fixed-point DSP implementation. In order to investigate this tradeoff, the speed- and the memory-conscious decoders are implemented. The maximum number of operations for the implemented speed-conscious decoder is 29.3 million cycles per second (MCPS) for a 32 kb/s bitstream. The maximum number of operations for the memory-conscious decoder, where 70% of the data are allocated to an external memory area, increases by 5.7 MCPS (19%) for the bitstream. The investigation of this tradeoff provides an actual relationship between the computational complexity and the internal memory size of the 3GPP enhanced aacPlus decoder. This relationship is useful for implementing a decoder with a best speed–memory balance that is determined by each specific application and the user requirements.