Fast Variation-Aware Statistical Dynamic Timing Analysis
Computer Science and Information Engineering, 2009 WRI World Congress（2009）
摘要
A statistical dynamic timing analysis framework is presented to study the impact of catastrophic defects and process variation on the delay behavior of a digital circuit considering the effect of gate switching on delays. It uses object-oriented programming and levelized code generation techniques to achieve fast runtimes with linear time complexity as the number of gates increases. The generated functional delay model along with experiments and statistical modules are compiled to machine code before execution; and random transition vectors approximate the delay profiles useful for virtual speed grading and yield estimation.
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关键词
circuit complexity,circuit switching,delay circuits,digital circuits,integrated circuit yield,logic CAD,logic gates,object-oriented programming,program compilers,statistical analysis,catastrophic defects,delay behavior,digital circuit,functional delay model,gate switching,levelized code generation,linear time complexity,machine code compilation,object-oriented programming,process variation,random transition vector,statistical module,variation-aware statistical dynamic timing analysis,virtual speed grading,yield estimation,Compiled Code Simulation,Dynamic Timing Analysis,Process Variations,Statistical Timing Analysis
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