Solving modern mixed-size placement instances

Physical design of modern systems-on-chip is extremely challenging. Such digital integrated circuits often contain tens of millions of logic gates, intellectual property blocks, embedded memories and custom register-transfer level (RTL) blocks. At current and future technology nodes, their power and performance are impacted, more than ever, by the placement of their modules. However, our experiments show that traditional techniques for placement and floorplanning, and existing academic tools cannot reliably solve the placement task. To study this problem, we identify particularly difficult industrial instances and reproduce the failures of existing tools by modifying pre-existing benchmark instances. Furthermore, we propose algorithms that facilitate placement of these difficult instances. Empirically, our techniques consistently produce legal placements, and on instances where comparison is possible, reduce wirelength by 13% over Capo 9.4 and 31% over PATOMA 1.0-the pre-existing tools that most frequently produce legal placements in our experiments.