A Neural Net Branch Predictor to Reduce Power

We present a power-aware neural network (PAN) branch prediction (BP) scheme for dynamic branch prediction, and schemes to incorporate anti-aliasing techniques into the neural branch predictor. We avoid incorrectly falling into segments of code that consume much power. By adding lookup table-based hardware, we estimate the power dissipated in the entire processor between successive branches. We consider a processor with a neural net branch predictor and use Aggressive Training on the neural network (NN) to severely penalize incorrect branch predictions that cause the processor to waste power. Our scheme dynamically learns to dissipate less power during successive calls to a particular branch instruction. Hence, our approach is different from all prior approaches that reduce miss-prediction or use hardware techniques (clock gating, banking) to reduce power dissipation.