A physical retiming algorithm for field programmable gate arrays

In this paper, we present a physical retiming algorithm for sequential circuits implemented in field programmable gate arrays (FPGAs). This algorithm can speed up the sequential circuits by reducing delay of all critical paths with negative slacks. By taking advantage of the physical information provided by placed circuits, this algorithm integrates two operations: retiming and register duplication. Retiming moves registers across combinational components. Register duplication moves registers across interconnect. Circuit functionality remains unchanged while performing these operations. A concept of timing budget is proposed to guide register moves. An accurate delay estimator for FPGA designs is developed to make register moves much more acceptable compared to conventional retiming technique. Experiments show that the physical retiming algorithm proposed in this paper can effectively reduce the critical path delays, increasing maximum frequency by 13.54%, on average, and improving by 59.54%, on average, the minimum slack for sequential circuits implemented in FPGAs.