Low-Cost and Highly Robust Quadruple Node Upset Tolerant Latch Design

This article proposes an exceptionally reliable and low-cost quadruple node upset tolerant latch (L C-QNUTL)suitable for the 65 nm CMOS technology. The innovative L C-QNUTL latch is primarily composed of three soft-error-immune(SEI) static random-access memory (SRAM) cells and a triple-level C-element (CE) unit, which includes five two-input CE and a clock-gating (CG)-based two-input CE. The SEI SRAM cell utilizes polarity hardening technology and source-isolation technology, significantly reducing the number of sensitive nodes and enhancing the latch's stability. By using the high-speed transmission gate (TG) technology and stacked structures, the proposed latch offers minimal overhead in terms of delay and power consumption, yielding an improved power delay area product (PDAP). When compared to contemporary quadruple node up set (QNU)-tolerant latch designs (including HLMR, 4NUHL,and LDAVPM), the new design offers substantial improvements-29.53% less delay, 80.09% reduced power consumption, 58.52%smaller silicon area, and 433.43% improved comprehensive PDAP on average. Furthermore, simulation results demonstrate that the L C-QNUTL latch exhibits reduced sensitivity to process, voltage, and temperature (PVT) variations, thus providing superior reliability, which makes it an ideal choice for safety-critical applications.