WeChat Mini Program
Old Version Features

Modeling the Operation of Charge Trap Flash Memory–Part I: the Importance of Carrier Energy Relaxation

IEEE Transactions on Electron Devices(2023)

Global TCAD Solut GmbH

Cited 2|Views18
Abstract
We present a novel approach to the modeling of carrier energy relaxation during high-field phases in semiconductor-oxide-nitride-oxide-semiconductor (SONOS) flash memory gate stacks. We show that this method integrates well with TCAD simulators and that taking the energy relaxation of carriers into consideration solves two of the most prominent problems of trapping layer dynamics modeling: The missing slope degradation in incremental step-pulse programming (ISPP) simulations and the incompatibility of the resulting charge distributions with long-term room temperature charge retention measurements. This article consists of two parts where this part discusses the physical/TCAD level. The second part derives a semianalytical model specifically for programming that reduces the numerical complexity while still retaining the main physical assumptions and the applicability to experimental data.
More
Translated text
Key words
Mathematical models,Tunneling,Programming,SONOS devices,Shape,Logic gates,Insulators,Charge trapping layer (CTL),energy relaxation,flash,incremental step pulse erase (ISPE),incremental step pulse programming (ISPP),semiconductor-oxide-nitride-oxide-semiconductor (SONOS),TCAD
PDF
Bibtex
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Data Disclaimer
The page data are from open Internet sources, cooperative publishers and automatic analysis results through AI technology. We do not make any commitments and guarantees for the validity, accuracy, correctness, reliability, completeness and timeliness of the page data. If you have any questions, please contact us by email: report@aminer.cn
Chat Paper
Summary is being generated by the instructions you defined