Insights into Scaled Logic Devices Connected from Both Wafer Sides

A. Veloso,G. Eneman,P. Matagne,B. Vermeersch,A. Jourdain,H. Arimura,B. O'Sullivan,R. Chen,A. De Keersgieter,E. Simoen,D. Radisic,Y. Oniki, A. Laffitte,S. Brus,E. Beyne,E. Dentoni Litta,N. Horiguchi

2022 International Electron Devices Meeting (IEDM)（2022）

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关键词

BS-only measurements,buried power rail trench-fin channel,DC characteristics,lower temperature FGA,reduced noise,scaled finFETs,scaled logic devices,self-heating impact,size 110.0 nm,size 2.0 nm,straighter fin profile,wafer sides,zero lateral distance

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