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    • Regeneration of Test Patterns for BIST by Using Artificial Neural Networks

    Tsutomu Inamoto,Yoshinobu Higami

    35TH INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUITS/SYSTEMS, COMPUTERS AND COMMUNICATIONS (ITC-CSCC 2020)（2020）

    Ehime Univ

    Cited 1|Views1
    Abstract
    In this paper, we display an approach to detect circuit faults by the built-in self test (BIST) technology. In the BIST for a certain circuit, it is usual to generate test patterns by feeding their seed values to a test pattern generator (TPG), which is contained in a device together with the circuit. It is ideal but impractical to make the device to contain a digital memory that stores effective test patterns. The key idea of the presented approach is to use the artificial neural network (ANN) as such memory on the expectation that an ANN can be implemented as an analog circuit. In addition, this paper investigates the inaccuracy that is inevitable regarding analog components.
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    Key words
    LSI testing,fault detection,BIST,artificial neural network
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