An FPGA Accelerator with Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization

Yuanmiao Lin, Zhaozhang Feng, Xueming Li, Hongmin Huang,Ruidian Zhan,Xianghong Hu,Shuting Cai,Xiaoming Xiong

IEEE Transactions on Circuits and Systems II Express Briefs（2025）

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Key words

Bit-level sparsity,mixed-precision,bit-serial computation,deep neural network,FPGA

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