Charge Trapping Challenges of CMOS Embedded Complementary FeFETs

In this work, we examine one of the important wear-out effects in metal-ferroelectric-insulator-semiconductor (MFIS) ferroelectric FETs (FeFET), comparing n-type and p-type endurance cycling degradation of the devices and propose a sloshing bathtub model as physical explanation for this effect. We show that: i) polarization (P FE ) switching is the main source of cycling degradation as demonstrated by severe V T -walkout through bipolar cycling with P FE switching pulses, while much less degradation without P FE switching, thus uni-polar pulsing, is observed; ii) comparing n-type and p-type cycling data, especially the n-type cycling degradation depends on the amount of interface trapped charge during the switching event, thus once ferroelectric (FE) bulk defects are fully charged up, electrons pile up at the FE/interlayer (FE/IL) interface, resulting in a steep V T increase; iii) a sloshing bathtub model is well-suited to explain the endurance degradation and can reproduce observed data; iv) this model can also explain a trapping artefact in HfO 2 -based MFIS/MFIM structures, often mistakenly interpreted as ferroelectric wake-up.