16.3 3nm Physical Unclonable Function with Multi-Mode Self-Destruction and 3.48×10^-5 Bit Error Rate

Silicon Physical Unclonable Functions (PUFs) generate secure encryption keys by exploiting random and unpredictable variations in the manufacturing process. However, achieving an acceptably low Bit Error Rate (BER) below 1×10 ^-4 remains a big challenge. Stable bit identification and masking of unstable bitcells [1, 2] enable a significant reduction in BER by eliminating bitcells that exhibit varying data outputs under different testing conditions. This is accomplished through the introduction of a controlled imbalance during the sensing (read) process, allowing the sense amplifier to detect weak bitcells that are likely to be susceptible to noise due to low read signal. In general, more signal (differential voltage or current) during sensing will result in fewer bit errors and enable the amplification of process variations and mismatches [3] to reduce the BER. This minimizes the need for area and power-intensive Error Correction Codes (ECC). Given the increasing security focus of advanced Systems on a Chip (SoCs), it’s becoming more common for PUFs to be used as the hardware root of trust. At the same time, PUFs have become a focus area of adversaries and researchers for tampering and reverse engineering of the secure key. Imaging techniques using Scanning Electron Microscopes (SEMs) have proven successful in reverse engineering Static Random Access Memory (SRAM)-based PUFs [4], potentially compromising the security measures within the system. Currently, there are a limited arsenal of tools available to counteract such tampering and thwart reverse engineering efforts.