A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications.

For the increasing demands in big data processing and cloud computing, today's mobile system has to meet the requirements of higher data bandwidth, lower system cost, and lower power consumption [1]. These requirements force dynamic random access memory (DRAM) to increase its data bandwidth and capacity with low power consumption, and are accelerating the movement from LPDDR5 to LPDDR5x for beyond-5G communications. For low power 8.5Gbps operation, 16Gb LPDDR5x DRAM I/O circuits using the 4 ^th -generation 10nm DRAM process are proposed in this paper. The proposed I/O improves signal integrity (SI) by using a self-pre-emphasized stacked driver in transmitter (Tx), a supply voltage insensitive data receiver in receiver (Rx), and an optimized clock tree in WCK clock-paths. The measured eye-widths of Tx and Rx, which are the indicators of SI, are 0.66 unit interval (UI) and 0.57 UI at 8.5 Gbps, respectively. Also, the measured power consumption is reduced by 20.0% compared to previous LPDDR5 SDRAM products [2].