Prototype Design of Global Common Module for ATLAS Experiment’s Phase-II Upgrade

A new Global Trigger subsystem will be installed in the Level-0 Trigger as part of the High-Luminosity Large Hadron Collider (HL-LHC) upgrade of ATLAS during the upcoming Long-Shutdown 3. It will feature new and improved trigger hardware and algorithms, and an increased maximum output rate of 1 MHz. The Global Trigger will run offline-like trigger algorithms on full-granularity data, gathered from several subdetectors and trigger processing subsystems. A single global common module (GCM) hardware is implemented across the Global Trigger system to be used as a multiplexer processor (MUX), global event processor (GEP), and global-to-central trigger processor interface (gCTPi). This common hardware platform method will minimize the complexity of the firmware and simplify the system design and long-term maintenance. The GCM prototype is a Advanced Telecommunications Computing Architecture (ATCA) front form factor board with two Xilinx Virtex UltraScale+ field-programmable gate array (FPGA) VU13P and one ZYNQ UltraScale+ FPGA ZU19EG and 17 25.78125-Gb/s FireFly duplex optical modules on it. The total power consumption of this board must be less than 350 W, and the temperature of the optical modules should be less than 70 °C in the worst case. The VU13Ps serve as algorithms processor nodes such as MUX, GEP, and gCTPi, and the ZU19EG with Peta Linux OS running on it is used as command/control/readout unit to configure and monitor the board and communicate with the ATLAS detector control system (DCS). The development of an ATCA blade with three large FPGAs and about 200 optical links running at 25 Gb/s is a very challenging task, and the successful test results have demonstrated this GCM prototype as an advancement of state-of-the-art electronics module design in high energy physics (HEP) experiments. This article presents the hardware design considerations, functionalities, and performance test results of this GCM prototype.