Reconfigurable Logic-in-memory Architectures Based on a Two-Dimensional Van Der Waals Heterostructure Device

Logic-in-memory architectures could be used to develop efficient computing devices with low power consumption. However, the approach is limited by device performance issues, including reliability and versatility. Here we report a two-dimensional van der Waals heterostructure device that can function as both reconfigurable transistor and reconfigurable non-volatile memory, as well as provide reconfigurable logic-in-memory capabilities. The architecture of the device—termed a partial floating-gate field-effect transistor—offers both charge-trapping and field-regulating units. When operating as a transistor, the device can be switched between the p- and n-type mode, and exhibits a subthreshold swing of 64 mV dec –1 and on/off current ratio approaching 10 8 . When operating as a memory, the device can be switched between the p- and n-type memory, and exhibits an erase/program ratio approaching 10 8 . We use the devices to fabricate complementary metal–oxide–semiconductor circuits, and linear and nonlinear logic gates with in situ storage, as well as device-efficient half-adder circuits.