Hierarchical parallel difference-equalization and channels regrouping based estimation of timing skew for time-interleaved ADCs

The timing skew mismatch decreases the dynamic performance of time-interleaved analog-to-digital converters (TI-ADCs). Some estimation methods need a given sequence between channels leading to a long operating time, while some digital skew estimation methods require multipliers, reference ADCs or FIR filters. This paper proposed a digital timing skew mismatch estimation method based on the hierarchical parallel difference-equalization and channels regrouping (HPDECR), requiring 3 (M − 1) adders and (M − 1) averagers without multiplier or FIR filter, speeding up the estimation process. The estimation method is adaptable for most correction methods and significantly immune to offset and gain mismatch effects. The method's effectiveness is proved by analyzing the ideal SNDR and SFDR with the first-order Taylor approximation-correction method. Simulations show that the proposed method can improve the SNDR 25.6 dB and SFDR 40.6 dB in 10 bit four channels TI-ADC. The measurement results improve the SNDR 11.3 dB and SFDR 21.9 dB in a commercial 12-bit 3.6-GS/s TI-ADC, proving the effectiveness and superiority.