Exploration and Optimization of Metal Gate Etch Back Process in Advanced Technology Node

Metal gate etch back process is involved in advanced logic technical node along with FinFET MOS structures in 16/14 logic technology node. Its principal function is etching moderate metal gate composing of TiN/TaN work function metal and W/HfO2 to constitute SAC (Self-Align-Contact) structure. The complex film stack with three-dimensional structure and four kinds of films makes this etch process more challenging than normal two-dimensional etch processes. The etch process is well-designed with etch/flush cycles to obtain ideal W/TiN/TaN/HfO2 profile. Creative design of etch process can achieve relatively independently etching of target film, aiming to accuracy control. Not only the difficult etch profile control of Short-Channel N/P MOS loading, but also the whole wafer uniformity and Short-Channel/Long-Channel pattern loading are very critical for process health. Due to different temperature sensitivity of complex metal gate film stacks, the temperature parameters of different etch step should be control specially to obtain optimized uniformity. Chemical reaction mechanism and physical bombardment mechanism are both playing important roles in SC/LC pattern loading. The systematic thinking of two mechanisms must be involved to decrease these loading as small as possible. Meanwhile, the polymer deposition mechanism also should be play considerable attention for its obvious influence in different patterns. In brief, metal gate etch back is complexity process for its various film stacks and three-dimensional structure. And systematic etch process control is challenging and achieved.