Rapid Prototyping Of Single-Photon-Sensitive Backside-Illuminated Silicon Avalanche Photodiode Arrays

We have developed a new approach for rapid die-level hybridization of backside-illuminated silicon avalanche photodiode (APD) arrays to CMOS readout integrated circuits (ROICs). APD arrays are fabricated on a custom silicon-on-insulator (SOI) wafer engineered with a built-in backside contact and passivation layer. The engineered APD substrate structure facilitates uniform APD substrate removal by selective etching at the die level after bump bonding. The new integration process has the following advantages over wafer-level 3D integration: 1) reduced cost per development cycle since a dedicated full-wafer ROIC fabrication is not needed, 2) compatibility with existing ROICs that are in chip-format from previous fabrication runs, and 3) accelerated schedule. The new approach is applied to produce 32x32 100-mu m-pitch silicon GmAPD arrays. Electrical performance of the APD arrays show 100% pixel connectivity and excellent yield before and after substrate removal.