A 16gb Sub-1v 7.14gb/S/Pin Lpddr5 Sdram Applying A Mosaic Architecture With A Short-Feedback 1-Tap Dfe, An Fss Bus With Low-Level Swing And An Adaptively Controlled Body Biasing In A 3rd-Generation 10nm Dram

The demand for mobile DRAM has increased, with a requirement for high density, high data rates, and low-power consumption to support applications such as 5G communication, multiple cameras, and automotive. Thus, density has increased from 2Gb [1] to 16Gb [2] in LPDDR4 and LPDDR4X, but the maximum density for LPDDR5 is only 12Gb [3] due to the limited package size specification: such as a 496-ball FBGA. In this work, a mosaic architecture is introduced to increase the density to 16Gb, even in a limited package size. Additionally, the I/O performance is improved by shortening the length for the top metal, and a short-feedback sense amplifier (SA) with dedicated VREFs for a 1-tap DFE. The side effect of a mosaic architecture is the performance of the internal DRAM due to a 1.64× long bus line; however, this is mitigated by a fully-source-synchronous (FSS) bus scheme that is robust to PVT variation. In addition, to reduce the power consumption of the long bus line a low-level swing (LLS) scheme is used in low frequency mode. Furthermore, to enhance power efficiency and yield an adaptive-body-bias (ABB) scheme is introduced in a 3rd generation of a 10nm DRAM process.