A Single-Inductor 4-Output Soc With Dynamic Droop Allocation And Adaptive Clocking For Enhanced Performance And Energy Efficiency In 65nm Cmos

Single-inductor multiple-output (SIMO) converters present a promising technology for enabling fine-grained supply-voltage $\\left(V_{\\mathrm{dd}}\\right)$ domains in SoCs. With efficiencies approaching those of buck converters, SIMO converters allow multiple domains to share a single inductor, thus reducing the use of bulky passive components [1–5]. However, SIMO converters suffer from a poor transient response and significant ripple, requiring extensive $V_{ {dd }}$ margining. Operation at an elevated $V_{ {dd }}$ -and, therefore, the load-current $\\left(I_{ {load }}\\right)$ - inflates power draw and further reduces system efficiency $\\left(\\eta_{ {system }}\\right)$, i.e. the ratio of the useful (margin-free) output power to input power draw.