A 3.0 TFLOPS 0.62V Scalable Processor Core for High Compute Utilization AI Training and Inference
2020 IEEE Symposium on VLSI Circuits（2020）
Key words
neural network topologies,dual-corelet architecture,many-core SoC,AI core,fp16 peak performance,high compute utilization AI training,inference,leading-edge compute efficiency,robust fp16 training,2-D systolic array-SIMD compute engines,architectural flexibility,compact DLFloat16 FPU,scalable processor core
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