FIR Feedback in Continuous-Time Incremental Sigma-Delta ADCs

In this paper, we present a new method to include finite-impulse-response (FIR) feedback digital-to-analog converters (DACs) in continuous-time (CT) Incremental Sigma-Delta (I-ΣΔ) analog-to-digital converters (ADC), which minimizes transient overshoots and thereby maximizes the modulator's stability. More specifically, it can be shown that increasing the number of FIR taps in I-ΣΔ feedback DACs could lead to instability or a reduced maximum stable amplitude (MSA), even when using a proper compensation path. However, by presetting the FIR feedback to a voltage close to the input signal, a larger number of FIR taps can be used, increasing the jitter robustness of the CT I-ΣΔ. This presetting is achieved using a low resolution Nyquist rate ADC to preset the FIR taps. Moreover, presetting the FIR feedback slightly increases the modulator's MSA and signal-to-noise ratio compared to a non-return-to-zero (NRZ) feedback. To validate the proposed presetting approach, a third-order I-ΣΔ-ADC employing a 12-tap FIR DAC with presetting using a 4-bit flash ADC is compared against a conventional NRZ DAC and a conventional FIR DAC without presetting in MATLAB/Simulink.