Optimization of short channel effect and external resistance on small size FinFET for different threshold voltage flavors and supply voltages.

In this paper, ideal Technology Computer Aided Design (TCAD) simulation is carried out for small size FinFET transistors. The definition of device critical dimensions is close to the 4th generation FinFET. The source/drain (s/d) extension doping is defined with certain gradient from epitaxy grown s/d, which is found to have dominant effect on the transistor electrostatic as well as the external resistance (Rext) between channel and s/d contact. The simulation is carried out for different threshold voltage (Vth) devices, which are, ultra-low Vth (ULVT), low Vth (LVT) and standard Vth (SVT), as well as different transistor supply voltages (Vdd). The extension doping gradient (sipgrdnt) is varied with the Rext and the sub-threshold swing (SSsat) with high drain voltage (Vd) monitored, which is a key indicator of gate electrostatic control on channel. All the comparison is performed at a given leakage current pre-defined for three Vth type devices by adjusting the metal gate work-function (WF). It is found that the Rext and SSsat are two competing factors for effective drive current (Ieff). Also, the SSsat for peak Ieff decreases with higher Vth flavor and lower operation Vdd and could be viewed as a guideline for FinFET optimization at this scaling regime.