Process and local layout effect interaction on a high performance planar 20nm CMOS

Fumihiko Sato,Ravi P Ramachandran,H Van Meer,Kyung Hwa Cho, A Ozbek, Xiangdong Yang,Yanbing Liu, Zengxia Li,Xiaojie Wu, Supriya Jain,Henry K Utomo,Uihui Kwon, Yeongmin Park,W L Tan, Xiangguo Dai,W Lai,Jungho Kim, David R Jones,Michael P Ganz,Doo Hwan Bae,Rosine Lallement,Sri Charan Vemula, Taekyoung Kwon, Peng Lee, Yaoyao Qi,M Weybright,Andreas Scholze,R Bingert, J King,M Sherony,Michael A Eller,Huiling Shang,K Tabakman,Vijaykrishnan Narayanan,Srikanth B Samavedam,R Divakaruni

VLSI Circuits（2013）

Cited 23|Views60

Key words

rmg,layout dependent device parameter shifts,sige,cmos integrated circuits,nfet/pfet boundary proximity,device performance improvement,embedded sige,high performance planar cmos technology,embedded processes,mobile performance planar cmos technology,low power mobile application,low-power electronics,ge-si alloys,boundary proximity,low power mobile applications,replacement metal gate,layout effect interaction,circuit operation,size 20 nm,smt,integrated circuit design,design style differences,esige process,process elements,gate pitch dependency,systematic device variability,integrated circuit layout,length of active area,stress memorization technique,layout dependent device parameter shift,local layout effect interaction,logic gates,stacking,low power electronics,metals,layout,stress

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined