Process Variation-Aware Task Replication for Throughput Optimization in Configurable MPSoCS
Electronic System Level Synthesis Conference（2012）
Key words
integer programming,integrated circuit design,linear programming,system-on-chip,ILP formulation,MPSoC system design,clock frequency,configurable MPSoC,configuration selection,data parallel task,delay distribution,die-to-die variation,frequency scaling,optimum load balancing,process variation-aware task replication,streaming pipelined MPSoC,system level throughput optimization,system timing yield,target timing yield,within-die variation
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