Quantitative Analysis For High Speed Interpolated/Averaging Adc

Interpolated flash ADC has been widely implemented in high-speed systems. However, practical design is really challenging and greatly experienced and trial-and-error oriented. This paper has quantitatively analyzed the resistive interpolation/averaging techniques and gave mathematical equations on how these two techniques affect the system's performance, like bandwidth and resolution. It also mathematically presents the system's offset voltages and variations that are caused by resistors mismatch when multiple interpolating stages are applied. This analysis can be used for trade-off consideration and hence optimum ADC design. The analysis is supported by simulation under SMIC 130nm CMOS technology.