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FPGA Implementations of the Round Two SHA-3 Candidates

International Conference on Field-Programmable Logic and Applications(2010)

Cited 123|Views1
Key words
round candidate,NIST Secure Hash Standard,computational efficiency,hardware interface,hash function,new hash algorithm,resource abundant environment,unit area,NIST-run public competition,Virtex-5 FPGA device,FPGA Implementations,SHA-3 Candidates
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