Monolithic 3D Macro Integrating CMOS with Ambipolar SONOS Tunnel FET for High Performance Edge-AI Computing Applications

P. H. Tseng, F. M. Lee, C. C. Yang, H. W. Chiang, C. T. Huang,Y. H. Lin,Yu-Yu Lin, N. C. Lin, P. J. Sung, C. T. Wu, W. F. Wu, C. H. Shen, T. H. Hou, A. Y. Wu, H. Y. Cheng, T. H. Yeh, M. H. Lee, K. Y. Hsieh

2025 IEEE International Memory Workshop (IMW)（2025）

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Key words

Tunnel Field-effect Transistors,Monolithic 3D,Data Storage,Fabrication Process,K-nearest Neighbor,Few-shot Learning,Drain Bias,Memory Window,High-performance Computing,Softmax Function,Channel Length,Matching Results,Gate Bias,Tunneling Current,Barrier Width

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