InterA-ECC: Interconnect-Aware Error Correction in STT-MRAM

Surendra Hemaram, Mahta Mayahinia,Mehdi B. Tahoori,Francky Catthoor,Siddharth Rao, Sebastien Couet, Tommaso Marinelli, Anita Farokhnejad,Gouri Sankar Kar

Design, Automation, and Test in Europe（2025）

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Key words

Error Rate,Bit Error Rate,Bitrate,Bit Error,Random Access Memory,Forward Error Correction,Parity-check,Correction Code,Spin Transfer Torque,Memory Technologies,Manufacturing Defects,Block Size,Error Detection,Resistant Parasites,Average Error Rate,Hot Zone,Extra Overhead,Memory Reduction,Cold Zone,Distinct Blocks,Block Error Rate,Rate In Zone,Error Correction Scheme,Extra Storage

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