A 28-Nm 9T1C SRAM-Based CIM Macro with Hierarchical Capacitance Weighting and Two-Step Capacitive Comparison ADCs for CNNs

Zhiting Lin, Runru Yu, Yunhao Li, Miao Long, Yu Liu, Jianxing Zhou, Da Huo, Qingchuan Zhu,Yue Zhao, Lintao Chen,Chunyu Peng,Qiang Zhao, Xin Li, Chenghu Dai,Xiulong Wu

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2025）

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关键词

Charge domain,computing-in-memory (CIM),hierarchical capacitance weighting (HCW),static random address memory (SRAM),two-step capacitive comparison analog-to-digital converter (ADC)

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