Cost-Performance Co-Optimization for the Chiplet Era

Alexander Graening, Darayus Adil Patel,Giuliano Sisto, Erwan Lenormand, Manu Perumkunnil, Nicolas Pantano,Vinay B.Y. Kumar,Puneet Gupta,Arindam Mallik

2024 IEEE 26th Electronics Packaging Technology Conference (EPTC)（2024）

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Key words

System Size,High-performance Computing,Figure Of Merit,System Configuration,Integration Scheme,Design Space,Early Design,Technology Node,Design Space Exploration,Configuration Options,Architecture Configuration,Design Process,Storage Systems,Organic Substances,System Architecture,Impact Of Size,Silicon Substrate,Cost Model,Power Estimation,Advanced Software,3D Stacks,Packaging Costs,Computational Core,Substrate Cost,Case Cost,Partition Size,Small Pitch

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