A 321-Layer 2tb 4b/cell 3D-Nand-flash Memory with a 75mb/s Program Throughput

Wanik Cho,Chanhui Jeong,Jongwoo Kim,Jongseok Jung, Keunseon Ahn,Jayoon Goo,Sangkyu Lee,Kayoung Cho, Tei Cho,Dauni Kim,Gwan Park, Yushin Ahn,Sooyeol Chai,Gwihan Ko, Sunyoung Jung,Eunwoo Jo, Taehun Park,Jinhyun Ban,Cheoljoong Park, Jae Hyun Park,Sanghoon Oh, Sojin Jeong, Youngjun Kwak, Kyungsoo Jeong, Jinyeop Kim, Minchol Shin, Eunho Yang,Taisik Shin, Youngil Kim,Jiseong Mun, Chanyang Ryu, Huihyeon Park,Changwan Ha, Jong Tai Park, Peng Zhang, Sooyong Park,Rezaul Haque, Hang Tian,Sunghwa Ok, Wonbeom Choi,Junyoun Lim,Dongkyu Yoon,Sechun Park,Wonsun Park,Kichang Gwon,Seungpil Lee,Hwang Huh,Woopyo Jeong,Jungdal Choi

IEEE International Solid-State Circuits Conference（2025）

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关键词

Density Data,High-speed Data,Relational Tables,Chip Size,Peripheral Circuits,Reduction In Leakage,Internal Voltage,Power Distribution Network,Charge Pump,Data Rate Increases,Feedback Factor

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