9.5 A Sub-1V, 50mv Dropout LDO Using Pseudo-Impedance Buffer with Phase-Margin Improvement Design
IEEE International Solid-State Circuits Conference（2025）
Key words
Aspect Ratio,Loading Conditions,High Gain,Comparison Table,Narrow Bandwidth,Bias Current,Output Stage,Light Load,Voltage Limit,Amplification Stage,Phase Margin,Gain Margin,Gate Capacitance,Ceramic Capacitors,Large Ripple,No-load Condition,Light Load Conditions,DC Gain,Current Mirror,Multi-stage Structure
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