Balancing Charge Loss and Carrier Mobility: A Multiscale Modeling Approach for Device Geometry Optimization of VS-DRAM Dual-Gate Access Transistors

Jun Deng, Xinhe Wang, Yangyi Ou, Z. Bai, Tun Wang, Xiaomeng Liu, Mingli Liu,Qi Hu, Xiangsheng Wang,Guilei Wang,Chao Zhao

IEEE TRANSACTIONS ON ELECTRON DEVICES（2025）

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关键词

Transistors,Random access memory,Scattering,Computer architecture,Geometry,Electrons,Semiconductor process modeling,Potential well,Logic gates,Silicon,Carrier mobility,channel thickness optimization,charge loss,multiscale modeling,vertically stacked dynamic random-access memory (VS-DRAM)

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