A Switched-Capacitor SRAM In-memory Computing Macro with High-precision, High-efficiency Differential Architecture
2024 50TH IEEE EUROPEAN SOLID-STATE ELECTRONICS RESEARCH CONFERENCE, ESSERC 2024（2024）
Key words
Computational Memory,Differentiable Architecture,Dynamic Range,Energy Efficiency,Finer Resolution,Matrix Multiplication,Weight Data,Clock Cycles,Quantization Noise,Pairs Of Columns,ImageNet Classification,Configuration Mode,Host PC
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