A low redeposition rate high density plasma CVD process for high aspect ratio 175 nm technology and beyond
San Francisco, CA（1999）
关键词
aluminium,encapsulation,integrated circuit interconnections,integrated circuit metallisation,integrated circuit reliability,passivation,plasma cvd,plasma density,sputter etching,voids (solid),0.2 micron,al rie technology,al-sio2,beol gap-fill,hdp-cvd process,aluminum line height,aluminum reactive ion etch technology,aspect ratio,current space aspect ratio,deposition temperature,deposition temperature constraints,first metal wiring level,front-end-of-line gap fill,high density plasma cvd process,interconnects,lithography shrinkage,minimum ground rule,redeposition rate,sheet resistance,stitched word line architecture,void formation,void-free back-end-of-line gap-fill process,reactive ion etching,front end,aluminum,high aspect ratio,etching,chemical vapor deposition,lithography
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