Design of CMOS Integrated Circulator Based On Sequentially Switched Delay Lines With Body-Floating and Clock Boosting Techniques

IEEE Transactions on Circuits and Systems II: Express Briefs(2024)

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Abstract
As the antenna interface of RF communication and radar systems, the performance of the circulator determines the quality of the whole system. This brief demonstrates a circulator based on sequentially switched delay lines with 6 transistor switches using body floating and clock boosting techniques to improve its linearity performance. The proposed circulator is fabricated in a standard 0.18 μm CMOS process, occupying an area of 1.7 mm2 including the pads, while consuming 34.9 mW at a supply voltage of 1.8 V, and these power dissipations are contributed by the LO path circuit. The measured Tx-to-ANT and ANT-to-Rx input 1dB compression points of the circulator are 13.44 dBm and 14.32 dBm, respectively, an increase of about 3.7 dB compared to the absence of these two technologies. The measured Tx-to-ANT and ANT-to-Rx insertion loss, and transmitter-to-receiver isolation are 5 dBm, 4.9 dBm, and >20 dB, respectively, for the frequency from 1.95 GHz to 2.55 GHz (with a relative bandwidth of 26.7%). And the measured ANT-to -Rx NF is 6.6 dB.
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Key words
Integrated circulator,CMOS,sequentially switched delay lines,linearity,body-floating technique,clock boosting technique
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